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Description
Jan 30, 2015 XC6SLX9 . ISE 12.4 v1.15. ISE 13.1 Update v1.18(7). ISE 12.3 v1.12(5). ISE 13.2 v1.07. XC6SLX16. ISE 12.1 v1.08. ISE 13.1 Update v1.18(7). Oct 25, 2011 Memory controller block support is x8 on the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the. May 12, 2014 NOTICE OF DISCLAIMER. The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx Jun 24, 2009 Density Migration on page 21, changed the required configuration memory size to 2.6 Mb ( XC6SLX9 ) and 3.6 Mb. (XC6SLX16). In Protecting Jun 19, 2015 02/16/2011. 1.5. Added BUFGMUX routing restrictions for DCM and PLL programming clock and. BUFGMUX ASYNC usage to Clock Buffers
| Part Number | XC6SLX92TQG144C |
| Main Category | Integrated Circuits (ICs) |
| Sub Category | Embedded - FPGAs (Field Programmable Gate Array) |
| Brand | Maxim |
| Description | IC FPGA 102 I/O 144TQFP |
| Series | Spartan-6 LX |
| Number of LABs/CLBs | 715 |
| Number of Logic Elements/Cells | 9152 |
| Total RAM Bits | 589824 |
| Number of I/O | 102 |
| Number of Gates | - |
| Voltage - Supply | 1.14 V ~ 1.26 V |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 85°C (TJ) |
| Package / Case | 144-LQFP |
| Supplier Device Package | 144-TQFP (20x20) |
| Image |  |
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